In order to explain the background of the invention, reference will be particularly made to FIG. 2.
FIG. 2(a) shows a static semiconductor memory device, in which the reference numeral 1 designates a memory cell, the numeral 2 designates a memory cell row including a plurality of memory cells 1, and the numeral 3 designates a row decoder constituted by NAND circuits and the like. The row decoder 3 applies a power supply voltage Vcc to a row selection signal line corresponding to the row address. The numeral 4 designates a row selection signal line, the numeral 5 designates a bit line, the numeral 6 designates a peripheral circuit, and the numeral 7 designates a bit line load transistor including some other circuits.
FIG. 2(b) is a timing diagram showing the row selection signal which is applied to memory cells 1 on a memory cell row 2 through a row selection signal line 4. The reference numeral 8 designates a row selection signal, the numeral 9 designates a reading-out period, and the numeral 10 designates a writing-in period.
The device operates as follows:
When none of the memory cells 1 are selected, all of the row selection signal lines 4 are at ground level. When a memory cell 1 is selected, the voltage of the row selection signal line 4 which is connected to the memory cell 1 rises to the power supply voltage Vcc by the row decoder 3. As a result, a memory cell row 2 including the memory cell 1 is selected.
When the memory cell row is selected, a column current flows from the power supply Vcc through the bit line load transistor 7 and the bit line 5 to the memory cell 1 in the selected memory cell row 2. This column current flows through the bit lines connected to all the memory cells of the selected memory cell row 2 during the period when the voltage of the row selection signal line 4 is equal to the power supply voltage. In order to reduce the current consumption, the row selection signal line 4 is made to rise to the power supply voltage level Vcc only during the reading-out period 9 and the writing-in period 10 of predetermined lengths so as to prevent the column current from flowing except for the reading-out and writing-in periods 9 and 10.
As described above, in this prior art semiconductor memory device, the row selection signal 8 is made to rise to the power supply voltage level during both of the reading-out and writing-in periods 9 and 10. In this device, however, the row selection signal 8 is made to rise to the power supply voltage level even during the writing-in period 10 regardless of the fact that the row selection signal 8 can be written in by a lower voltage than the power supply voltage, which results in a wasteful power consumption of the column current to the extent that the voltage of the row selection signal exceeds the maximum required voltage.
Another prior art semiconductor memory device is disclosed in an article "A 64Kb CMOS RAM", by Satoshi Konishi et al., ISSCC Digest of Technical Papers (1982). In this 64Kb CMOS RAM, a change of address is detected to generate an internal clock and to precharge the bit lines by one-shot pulses, thereby reducing the DC current in the memory operation.
Another prior art semiconductor device is disclosed in an article "A 20 ns 64Kb CMOS RAM", by Osamu Minato et al., ISSCC Digest of Technical Papers (1984). In this article, the change of address is detected to generate an internal clock and to thereby make the word line level operate in a clockwise manner, thereby reducing the current consumption in the memory operation.